Flash 4 Click Board™

Product Code: MIKROE-3191

The S25FL512S module can withstand up to 100,000 program cycles, with the data retention period of minimum 20 years. The flash memory IC used on the Flash 4 Click Board™ features Serial Flash Discoverable Parameters (SFDP) mode, used to retrieve the advanced information from the device, such as the operating characteristics, structure and vendor specified information, memory size, operating voltage, timing information, and more. Featuring both normal and double data rates over the standard, Dual/Quad SPI interface, the improved reliability of the stored information by utilizing the hardware Error Correction Code (ECC) generation, One-Time Programmable (OTP) memory block of 1024 bytes, an advanced sector protection, AutoBoot, and much more, this Click board™ is a perfect solution for the mass storage option in various embedded applications. Due to its fast performance, the Flash 4 Click Board™ can also be used for the code shadowing, execute-in-place (XIP), and data storage. An additional level translator IC allows the Flash 4 Click Board™ to be used with a wide range of MCUs, operating both with 3.3V or 5V logic levels.

How Does The Flash 4 Click Board™ Work? The Flash memory module used on the Flash 4 Click Board™ is the S25FL512S, a 512 Mbit SPI Flash memory module, from Cypress. The Flash memory density is usually expressed in bits, so 512 Mbit of memory aligned in 8 bits long words, translates to a capacity of 64 megabytes (MB). This memory module contains 256 sectors of 256 KB each. Furthermore, the memory is organized in 256KB sectors that alow user to erase whole sector only and write up to 512byte at a time. The advanced MirrorBit® technology allows storing of two data bits in each memory array transistor (memory cell), effectively doubling the capacity of a single storage cell this way. The Eclipse™ architecture is responsible for the greatly improved erase and programming performance, compared to other Flash modules of the previous generation. Due to a higher speed, an execute-in-place (XIP), as well as the data shadowing is possible with the Flash 4 click. The S25FL512S flash module supports the standard SPI interface, but it can also optionally use the Dual and Quad SPI interface, allowing the full data transfer rate of 80MB/sec to be achieved. In addition, the flash module supports DDR read commands in all SPI modes, using both clock edges to transfer the data (data transfer is performed on both the rising and the falling edge of the clock). A typical communication procedure consists of sending a proper instruction (command) from the host MCU via the SPI interface, followed by either an address, data, or both, and a response from the S25FL512S flash module, which can be either a stream of data or a single byte, depending on the command received. One of the key features of the S25FL512S is certainly the AutoBoot feature. It allows the module to automatically initiate the memory transfer from the predefined location (memory read operation) after the reset cycle. Considering a typical communication scenario, where READ command followed by the one or more address bytes need be used, AutoBoot allows the host MCU to pull down the #CS (Chip Select) pin and start receiving a data stream over the SPI interface for as long as the #CS pin is held LOW, without any wasted cycles. As soon as the #CS pin is released, the S25FL512S returns to a normal operation. The Advanced Sector Protection (ASP) is a powerful protection model that incorporates a set of various software and hardware methods to enable or disable programming or erase operations within a sector or an entire memory. A specialized ASP OTP register offers a password protection mode or a persistent protection mode, allowing an increased flexibility of the protection. Using the OTP memory allows the protection mode to remain in place for the whole life-cycle of the device. The #WP write protect pin is used to put the device into the hardware write protect mode. A LOW logic level on this pin prohibits write operations to the Block-Protection bits of the Status register. Locking down the Status Register will block changes of the Status Register Write Disable (SRWD) bit, which is required for the Write and Erase operations, effectively preventing the memory content changes. The pin is multiplexed with the IO2 function, therefore it is not available when Quad SPI is used The #HOLD pin is used to hold the data transfer. When the Chip Select pin (#CS, routed to the mikroBUS™ CS pin) is set to a LOW logic level, the data transfer will be put on hold when the LOW logic level of the serial clock coincides with the falling edge of the #HOLD pin. Similarly, resuming the data transfer will happen when the LOW logic level of the serial clock coincides with the rising edge of the #HOLD pin. The pin is multiplexed with the IO3 function, therefore it is not available when Quad SPI is used The SPI interface pins are routed to the mikroBUS™ so that the inter